This invention relates to packaging of semiconductor chips, and more particularly, to a chip package wherein the substrate is provided with a repeating pattern of conductor ends, with each pattern defining sites to permit the reception of a variety of different chips. The conductor ends are wired to connect both within the same pattern and with adjacent patterns. This permits the personalization of a common substrate to receive many different combinations of chips.
In the evolution of semiconductor technology, packaging of the chips has taken on increasing importance. The number of circuits that can be placed on a chip has dramatically increased as has the number of functions of any given chip. There are chips which are primarily memory, those which are primarily logic, and those which are mixed logic and memory. As miniaturization progresses it is becoming increasingly desirable to place a number of different chips, and different combinations of chips onto a single substrate. This chip/substrate package can be inserted as a unit into various pieces of equipment.
However, with prior art technology each module having a different combination of chips had to have a substrate designed specifically for each combination of chips. Indeed, even in a single chip module, each different chip required a different substrate unique to the given chip. Prior art examples of technology for providing a substrate for a given chip or specific combination of chips is represented in U.S. Pat. Nos. 4,202,007 and 4,193,082 which represent one technology for making substrates with buried wiring, and IBM Technical Disclosure Bulletin, Vol. 22, No. 5 dated October 1979, at pages 1841-1842, which represents a different technology. This prior art, however, shows only a technique for forming substrates which will accept predetermined chips or chip combinations. The necessity of designing, producing and stockpiling a different substrate for each chip and each different combination of chips is very expensive and adds significantly to the cost.